Product: Sapphire Radeon HD5770
Company: Sapphire
Authour: James 'caveman-jim' Prior
Editor: Charles 'Lupine' Oliver
Date: October 13th, 2009
Core Architecture

ATi Radeon
ATi Radeon
The Juniper core architecture is similar to half of one Cypress core. The chip contains 1.04 billion transistors and is manufactured on a 40nm process and The Terascale 2 unified processing architecture is scaled back from Cypress' 20 SIMD units.

For the HD5770 this means 10 SIMD - 800 ATI Stream processing units, 40 texture units (four per SIMD), and 16 Color ROP units and 64 Z/Stencil ROPs; in the HD5750 there are 9 SIMD units and thus 720 stream processors and 36 texture units but the same 16 ROPs for 64 Z-samples and 16 Blends per cycle.

Juniper also features half the memory interface of Cypress with a 128-bit GDDR5 memory interface to deliver up to 76.8GB/sec of bandwidth. Juniper retains the Evergreen family feature Error Detection Code hardware (EDC) that performs CRC checks on data transfers for improved reliability.

The HD5770 engine is clocked at 850Mhz and the memory at 1200Mhz to deliver 1.36TeraFLOPS, approximately the same as the previous generation high end, the HD4890. The HD5750 engine is clocked at 700Mhz and 1150Mhz memory clock, for a compute power of almost 1.01TeraFLOPS, a little higher than the HD4850.


[ Juniper Architecture ] [ Cypress Architecture ] [ HD5770 vs HD5750 ]

As before, Juniper features multi-sampled anti-aliasing and Evergreen's new anisotropic filtering method for increased image fidelity. Edge detection and adaptive modes are still present, along with ATI's new rotated grid super sampling anti-aliasing mode. LoD settings are being considered as possibly being required to offset the blurring of box filters with a negative bias.

The cards feature PCI-Express 2.1 x16 interfaces. PCIe 2.1 offers several new features that could be leverage for better performance for specific applications, including:

  • Internal Error Reporting - Make internal errors visible to software; Corrected and Uncorrectable.

  • Atomic Operations - Support SMP-type operations across a PCIe network to allow for things like offloading tasks between CPU cores and accelerators like a GPU.

  • Resizable BAR capability - allow the system to select how much system resource is allocated. Ideally, the software would use the largest setting reported, since that would give the best performance, but it might choose a smaller size to accommodate constrained resources. Currently, sizes from 1MB to 512GB are possible.

  • Dynamic Power Allocation - Provide more software-controlled power states to improve power management.

  • TLP Processing Hints - Improve memory latency by associating a packet with a given processor cache.


content not found


Copyright 2021 © Rage3D.com

You may not use content, graphics, or code elements from this page without express written consent from Rage3D.com

All logos are trademarks of their original owners. Used with permission.