Product: AMD 790GX Chipset
Company: AMD
Authour: Alex 'AlexV' Voicu
Editor: Charles 'Lupine' Oliver
Date: November 13th, 2008
SB750 - Southern Hospitality

Many things could be said about the SB600, ATI/AMD's last southbridge before SB750 (we'll ignore SB700 as that was not a full step in the right direction, in spite of being an improvement), many of which would be mean and require using 50 Cent worthy expressions. What was wrong with it, you ask?

  • Limited SATA connectivity - only 4 SATA ports supported

  • Problematic AHCI - probably also due to its lack of support for 64bit DMA combined with it reporting to the OS that support is present

  • RAID limitations - RAID levels 1, 0 and 10 only, with the rather popular 5 mode conspicuously absent

  • Vista+SB600+ some (many) hapless Phenoms:

Why blame the SB600 Southbridge for that? After all, that blue-screen can happen without it being anywhere near - under certain circumstances (insufficient voltage being delivered to the CPU) Intel boards get it as well. Whilst that is correct, seldom does one get it when operating at stock on non-SB600 boards - for example, our 9850 that would only function if underclocked with the MSI K9A2, with even the slightest upwards adjustment of the multiplier causing the above marvel of white and blue to conquer the screen, and stock operation being unstable at best. Getting a 9950, we had better luck ... so dud CPU, right? That might've explained it, until we plugged the 'faulty' 9850 into one of the 790GX boards and found it to be stable.

Another data point supporting the aforementioned BSOD-SB600 link is the ill-fated DFI ICFX2300, which was based on the RD600-SB600 combo, the last Intel board with an AMD chipset. That one was a nightmare as soon as one installed Vista ... it seemed as if clock interrupts were never received! The sole common point between that rather old Intel board and newer 790FX AMD boards is SB600.

To be completely accurate though, the problem is likely caused by a rather complex CPU-clock generator in NB-SB-AMD driver(s) interaction, with the SB600 being the weakest link. Now, after that rather long innuendo, what's up with the new SB750 and how does it patch things up/improve?

  • Natively supports 6 SATA ports (not necessarily impressive, but an improvement nonetheless), whilst also adding support for RAID 5

  • AHCI actually works properly this turn (at least it did in our experience, even when using SATA optical drives)

  • USB 2.0 connection count is bumped up from 10 in SB600 to 12

  • it adds secret sauce:

Something that's advanced, and handles calibration of clocks must be really good, right? It actually is to a great extent, although it's not entirely clear how it works its magic (and getting an answer from AMD is ... difficult). The biggest benefit it brings, in our opinion, is not the improved overclocking headroom, although that's what's advertised/touted everywhere since it's bound to draw a lot of attention, but its bringing of stability at stock settings to all Phenoms, hapless or not. Remember the troubled 9850 from before? Plug it into a SB750 equipped board, set ACC to auto, and say "au revoir" to the dreaded BSOD ... even a 200 MHz OC becomes a possibility, on stock settings. Fiddle with ACC a bit, and the OC grows to 400 MHz - Noaicee!

Since AMD was reasonably cagey when we approached them about the "A clock interrupt request ..." error, it's not likely they'll advertise that one of the benefits of ACC is doing away with that. However, this is a biggie, because in order to run you must at least be able to sustain your own weight - which means that OC'ing becomes relevant only after stock stability has been achieved.

As for the OC’ing boost, it is indeed there, to a greater or lesser extent, depending on how bad or good your CPU is. We'll discuss this in more detail once we've properly introduced the boards.

What we know about ACC operation is this:

  • setting it to Auto means setting it to +2% on all cores

  • values over +6% are recommended once higher voltages are used (1.5v CPU VID and higher)

  • negative values should allow for lower operating voltages at stock

  • different CPUs like different values, so you'll have to fiddle a bit, simply leaving it on Auto may not always be optimal

AMD says that the Southbridge hooks into the CPU via a direct interface, with exact details considered Intellectual Property and not fully disclosed for competitive reasons. Peeking at an nVidia slide that was published by expreview.com a while ago (http://en.expreview.com/2008/08/20/nvidia-mcp7278-will-support-acc-overclocking.html), it seems that this happens via the JTAG interface found on Phenoms.

Something also relatively known, if one knows where to look, is that AMD had intended to add an internal clock generator to SB700, but ran into issues which required motherboard makers to use an external one instead; the SB750 solves this, as did a cancelled prior iteration codenamed SB710, which may be another piece in the SB750-ACC-better overclocking/stability puzzle.

After talking with a very smart Friend, we've come up with two possible ways in which ACC might interact with CPUs to produce the results seen since its introduction (it's a one or the other situation, albeit the second proposal would indirectly involve affecting the first aspects as well):

  • Change parameters dealing with asynchronous clock domains within the chip/clock crossing, by increasing/reducing the number of sync clock cycles - this would correlate nicely with the increased OC’ing headroom aspect, as well as provide anecdotal evidence that indicates higher ACC values induce a slight reduction in performance in something like Prime 95, the core with the highest ACC modifier finishing last, whereas the opposite holds true for negative ACC values, in which case the core with the lowest ACC value finishes first - however, more testing is required to fully verify this.

  • Adjust skew/clock slew/ drive strength (adjusting drive strength affects clock slew anyhow) - this possibility correlates with the fact that "weak" CPUs seem to receive the most benefit, whilst good CPUs get almost none, whilst also explaining why extreme ACC values can cause boot failure, and why high positive values are recommended for high voltages (albeit it's hard to know what it is you're adding X% to)

Be aware that the above are at best slightly educated guesses ... there simply isn't enough data out there to deduce exactly what's going on. For all we know, miniature dwarven craftsmen could travel via the SB-CPU link to tweak the latter - at this point in time, the exact mechanism remains a mystery. However, for most people the only thing that will matter is that it pretty much works.


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