Eric Demers and GCN, Part II



Company: AMD
Author: James Prior
Date: December 22nd, 2011

384-bit Bus and Product Scaling

R3D: How much arguing was there about 256-bit vs. 384-bit bus?

Eric: I think we were arguing yesterday about it! [laughing]

Eric: We run through many different configurations, how many CUs do you have, how many ROPs do you have, how much memory bandwidth do you have; what's the cost of all of these? It's not pure science, regretfully, there's a certain artistic aspect

Tom: There's a little bit of math involved. [laughing]

Eric: A little bit of math, a little bit of science, because sometimes you can't anticipate the future applications either and we just look at the sweet spot of all of these. There's also psychological pressure, where people say 'why don't we put larger framebuffers?' - that sells, the number itself sells sometimes as well. There are all these factors that come into it. It ended up being that if we really wanted to push up the CU count from the 6970 and/or the ROP count, we needed more memory bandwidth. Pushing the speed the up, we could have done that, maybe going to 6GHz, 6.2GHz or something - I mean that would have taken us from 155gbps to maybe 185/190gbps; now we're up to 260gbps. It's a huge uplift and it's got 50% better; it was the best thing to do for this part.

R3D: How granular can you be with disabling parts, can you get down to a 320-bit with reduced number of cores inside each CU?

Eric: : We don't have per channel selectivity but there are a lot of configurations, certainly 256-bit and 128-bit. I don't know that we'd do a 128-bit. There is some flexibility there, that the Tahiti Pro will take advantage of, if they so decide.

Eric: The CUs themselves, the whole thing is very scalable, you can disable CUs one after another and you can improve yield that way. Let's say you have one bad CU, well it's not a 7970 anymore, but maybe it's a 7950? We will scale CUs, don't know if we'll scale ROPs.

Tom: We have redundancy there anyway.

Eric: Yeah, we have redundancy there, and I think we will be scaling the memory but I'm not 100% sure.

Tom: Yeah, it's pretty sure.

Eric: You'll get the 7950 specifications soon enough, it's a business unit decision not so much ours. We try to put in a much flexibility into the design, but that doesn't mean the business unit will leverage all of it, always.

Tom: With a new process you have to be a little more aware of the range of yields and having the skew options to [deliver products]. As the process gets more mature you can maybe not have as much overhead for dealing with constraints.

Eric: They do have performance goals for all the parts, they won't just turn off everything.

Tom: [laughing] Those yield really good!

Eric: Yeah, those yield great! [Laughing] Those guys have some specific performance targets for every single SKU, and that's how they're gonna do it, and they're gonna play those games to improve yield by using redundancy and reduce cost, but still deliver performance levels they require. I don't know if there are any other 7900 series planned, but at least the Pro version you'll get their best guess at the configuration. I don't know exactly what they're going to do with the frame buffer but it is flexible.

Tom: In general the 28nm yield is doing well, we're happy with what we're seeing [laughing]. We've gone through many process node transitions, we've always been [first] and so we're pretty good at predicting and running.

Eric: We'd prefer it to be $12 by the way [laughing, holding Tahiti XT chip], but it is doing better than we feared, but it can always do better. It's pretty though.

AMD's Southern Islands Tahiti Chip

R3D: It does look pretty cool, glad there's no heatspreader on it.

Eric: Yeah, that's the stiffener ring. The other one was just a rectangle, and it would warp sometimes [miming twisting along plane of chip]. This one has stiffeners which make it a little more complicated but make it warp less.