Company: AMD
Authour: James Prior
Editor: Charles Oliver
Date: August 24th, 2010
Bobcat

Bobcat is the other new architecture talked about in today's Hot Chips presentation. The ethos for Bobcat was slightly different than Bulldozer; where Bulldozer is the heavy lifter, Bobcat is the small efficient and low power native dual-thread x86 core. Both are critical to AMD's ongoing success.

Bobcat Module
Bobcat Module

Bobcat cores are dual x86 decode and out-of-order instruction and load/store engines with complete instruction set extension support - SSE1/2/3, SSE3 and Secure Virtualization. Bobcat cores are not designed for ultimate outright performance, but for efficiency and scalability - offering an estimated 90% of the today's mainstream performance in less than half of the same silicon area. Bobcat, like Bulldozer, has clock and power gating with system low power states to keep platforms based on the dual-core running efficiently and cheaply.

Bobcat Block Diagram
Bobcat Block Diagram

The headline grabbing sub one-watt capabilities won't be seen until later in the product cycle, where form factors and market needs are identified to take advantage of it.

As part of AMD's design company ethos, Bobcat cores are fully synthesizable and easily portable across different process technologies - great for moving to different foundries and process technologies, and customizing the different partners' needs. Initially Bobcat cores will be seen in the new notebook Accelerated Processing Unit codenamed Ontario, due in 1H 2011.

Fusion APU Ontario

The Ontario Accelerated Processing Unit (APU) features the Bobcat core in combination with programmable graphics processor (GPU) architecture - an array of SIMD (Single Instruction, Multiple Data) units, for processing highly vectorized workloads.

Ontario FUSION APU
Ontario FUSION APU

x86 architecture instructions extension like SSE support vectorized code, but offer little parallelism. AMD have SIMD units inside the HD 2000, 3000, 4000 and 5000 series, based on their basic building block of a Vec5 thread processor. The thread processors are comprised of four stream cores and one special function unit. These are then grouped in bunches of sixteen to make a single SIMD unit, the smallest granular design block for AMD's Graphics Processors.

Evergreen Series 'Vec5' Thread Processor
Evergreen Series 'Vec5' Thread Processor

Recently, it was disclosed that there will be up to 480 stream processors in the FUSION APU. 480 stream processors, if grouped in sixteens, give six SIMD arrays. Examining the AMD ATI Radeon product stack, that compares favorably with all the mainstream GPUss, from the HD 5450 (1 SIMD, 80 SPs), to the HD 5500/5600 series (5 SIMD, 400 SPs). Also present in the discrete and current IGP solutions is the Universal Video Decoder (UVD). The presence of a native UVD should make the explosion of online and local HD content even more exciting, as it can seamlessly accelerate video encoding and decoding for many popular video formats (MPEG-2/4, AVC, VC-1, Flash). Possible enhancements for this are to hardware accelerate VP8, the codec behind the new WebM video standard for HTML5. This will likely debut in the next generation of discrete cards first, as part of UVD 3, with APU adoption at the next product cycle refresh.

The biggest unknowns are core clock speed and ROP/Texture Unit counts, as these will define the performance of the Graphics Processor, along with details of the memory. While we know the memory will be DDR3, we don't know if it will be a portion of system RAM allocated at POST, or dedicated mainboard graphics RAM (possibly faster and lower latency but at the expense of power savings). We can speculate there will be 20 Texture Units, based on the Evergreen architecture of 4 TUs per SIMD, and 8 ROPs and a clock speed of around 400-500MHz, to meet thermal design parameters. Finally, we also don't know how the HD 5000 lack of sideport will affect performance, as previous Integrated Graphics Processors (IGP) have leveraged sideport dedicated mainboard memory to great effect.

Llano, The First APU

AMD Llano APU
AMD Llano APU

The first combined CPU and GPU Accelerated Processing Unit products will appear late this year with Llano, a 40nm process based product targeted at both mainstream desktops and notebooks. It will feature existing technology from AMD's CPU and GPU line, with DirectX 11 graphics as part of the processor, and a monolithic die but not integrated to the level of Ontario's FUSION APU. This APU will pave the way for the low power Ontario APU. If Black edition APU processors are forthcoming, it will be interesting to see if they offer a method for adjusting the GPU core clock independently of the processor core clock, either by multiplier control or separate base-clock.


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