ADFS 2011 Wrapup & AMD Lynx Platform Tests

Company: AMD
Author: James Prior
Editor: Charles Oliver
Date: July 18th, 2011

Keynote: Fusion System Architecture

Now that you've got an overview of the platform and technology, let's cover some salient points from the AMD Fusion Developer Summit keynotes.

Fusion System Architecture - Phil Rogers

The first keynote of the inaugural AMD Fusion Developers Summit was presented by AMD Fellow Phil Rogers, and was catchily titled The Programmers Guide to the APU Galaxy. Certain people in AMD are big fans of Douglas Adams, and every once in a while a product or presentation slips in a reference to the inaptly named trilogy, such as the card codenamed Trillian - the AMD ATI Radeon HD 5870 Eyefinity 6 edition.

The presentation was very well made and had a feel akin to some of the Eric Demers technical presentations we've seen before - as it turns out, some of it was from AMD CTO for Graphics, Eric Demers, and 'borrowed'' by Phil for his talk. The 45-minute keynote passed quickly thanks to a fast, metered pace and effective use of slides. As is now usual for AMD presentations, the environment was dominated by a huge video projected backdrop, creating using three high definition projectors in Eyefinity.

As the title indicates, the keynote was for developers. It was certainly technical in several places, but was mostly aimed to be strategic and show how Accelerated Processing Units (APUs) will be able to provide 'a supercomputer in a notebook'. AMD's A-series APUs for mainstream desktops and notebooks incorporate discrete level graphics with four x86 cores, combing scalar processing on the CPU with parallel processing on the GPU with high-bandwidth access to memory. Future developments include making the APU easier to program and optimize, as well as updating the hardware to increase performance and lower power.

Hetergeneous Systems Era

After giving an overview of the Bobcat architecture based APUs for ultra-portables and tablets (yes, AMD has an APU suitable for use in a tablet - the Z-series, platform codename Desna), Phil gave a brief overview of the Llano APU. The key to its suitability for GPGPU is the shared memory access now made possible by the shared memory controller. As a fundamental system device, the x86 cores have demand based paging where the GPU relies on scheduled access, controlled by the OS. Using handles to pass GPU pointers to the CPU and vice versa, slow copy operations can be avoided so that the CPU can prepare memory for the GPU cores to operate on and then access the results once the GPU compute operation is complete. This is a big step forward in ease of use, and shows why some other GPU compute API's were used only to provide atmospheric or eye-candy level additions to games, rather than being a fundamental game changer. Having the GPU and CPU physically so close together and present in all AMD's mainstream and value product lines gives a solid common denominator.

Evolution of Hetergeneous Computing

Most of the keynote was spent fleshing out how the future of APUs will come to be, and how more and more programmable and accessible the raw horsepower will be. This was a crucial move for AMD, which showed their need for developer adoption, willingness to be (somewhat) transparent and show that companies now can invest time and effort into OpenCL and not get their legs jerked out from under them in 2 years when the product line-up changes again. On that front, AMD was very focused on talking about how to get developers using OpenCL to make money by creating great products. This is a refreshing change, focusing on making a better product using the new technology rather than the technology for its own sake.

Fusion System Architecture Roadmap

The Fusion System Architecture (FSA) is proposed by AMD to be an open platform with published specifications, to be ISA agnostic for CPU and GPU. It is intended to provide a platform for OpenCL to run on, and allow the use of any vendor's hardware in the architecture. This is the major announcement of the keynote, and is really the key to why ARM was invited to speak. ISA agnostic means that FSA was not intended to lock in AMD CPU/GPU/APU technology, but allow mix'n'match of different technologies, perhaps a little ARM core here, a little SIMD array with special functions on it over there.

FSA Intermediate Layer

On top of FSA, AMD is aiming to provide an intermediate layer, known as FSAIL. Yes, the Fusion System Architecture Intermediate Layer, and it's a lisping troll's dream, but it's designed to use a just-in-time compiler (or finalizer) to take parallel programs from the managed/interpreted code level down to the ISA (x86, Radeon Cores, etc.) used in the specific FSA implementation. FSAIL also seeks to provide support for debugging, interrupts, exceptions and offer syscall methods to directly talk with system services.

FSA Memory Model

Alongside FSA and FSAIL comes the most important part, the memory model. Here, AMD is talking about compatibility, with popular programming languages, but also offering consistency for parallel compute tasks. Coherency and visibility were big topics, as these are needed to give more performance, easier tuning, and better quality code. An interesting tidbit here was that ARM will provide 64-bit support for FSAIL and APUs, as FSAIL is inherently 64-bit with 32-bit running on top.

Overall the Programmer's Guide to the APU Galaxy appeared to be very well received by the press and attendees - AMD hit the target audience on the head with their level of technicality and disclosure of road map and use cases. AMD was clear that the tools and platform for everyday and hobbyist programmers aren't there yet, currently bigger budget companies and extraordinary programmers are blazing a trail in using OpenCL to provide heterogeneous compute applications today.

Chuck Moore & Phil Rogers at post keynote Q&A